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- Author - Derek Winnert
- Bio Derek Winnert is a leading UK film critic and author, and a member of the London Critics Circle.
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Free download chui shao renovation. You have an amazing voice. 5,2 ... We use cookies to offer you a better experience, personalize content, tailor advertising, provide social media features, and better understand the use of our services. To learn more or modify/prevent the use of cookies, see our Cookie Policy and Privacy Policy. Due to its high intrinsic mobility, germanium (Ge) is a promising candidate as a channel material (offering a mobility gain of approximately ×2 for electrons and ×4 for holes when compared to conventional Si channels). However, many issues still need to be addressed before Ge can be implemented in high-performance field-effect-transistor (FET) devices. One of the key issues is to provide a high-quality interfacial layer, which does not lead to substantial drive current degradation in both low equivalent oxide thickness and short channel regime. In recent years, a wide range of materials and processes have been investigated to obtain proper interfacial properties, including different methods for Ge surface passivation, various high-k dielectrics and metal gate materials and deposition methods, and different post-deposition annealing treatments. It is observed that each process step can significantly affect the overall metal–oxide–semiconductor (MOS)-FET device performance. In this review, we describe and compare combinations of the most commonly used Ge surface passivation methods (e. g. epi-Si passivation, surface oxidation and/or nitridation, and S-passivation) with various high-k dielectrics. In particular, plasma-based processes for surface passivation in combination with plasma-enhanced atomic layer deposition for high-k depositions are shown to result in high-quality MOS structures. To further improve properties, the gate stack can be annealed after deposition. The effects of annealing temperature and ambient on the electrical properties of the MOS structure are also discussed. Germanium surface passivation and atomic layer deposition of high- k dielectrics—a tutorial review on Ge-based MOS capacitors This article has been downloaded from IOPscience. Please scroll down to see the full text article. 2012 Semicond. Sci. Technol. 27 074012 () Download details: IP Address: 157. 193. 57. 72 The article was downloaded on 26/06/2012 at 09:57 Please note that terms and conditions apply. View the table of contents for this issue, or go to the journal homepage for more Home Search Collections Journals About Contact us My IOPscience IOP P UBLISHING S EMICONDUCTOR S CIENCE AND T ECHNOLOGY Semicond. 27 (2012) 074012 (14pp) doi:10. 1088/0268-1242/27/7/074012 Germanium surface passivation and atomic layer deposition of high- k dielectrics—a tutorial re view on Ge-based MOS capacitors Qi Xie 1, Shaoren Deng 1, Marc Schaekers 2, Dennis Lin 2, Matty Caymax 2, Annelies Delabie 2, Xin-Ping Qu 3, Y u-Long Jiang 3, Davy Deduytsche 1 and Christophe Detavernier 1 1 Department of Solid State Science, Ghent University, Krijgslaan 281/S1, B-9000 Ghent, Belgium 2 IMEC, Kapeldreef 75, B-3001 Leuven, Belgium 3 State Key Laboratory of ASIC and System, Department of Microelectronics, Fudan Univ ersity, Shanghai 200433, People’s Republic of China E-mail: Received 20 January 2012, in final form 20 April 2012 Published 22 June 2012 Online at Abstract Due to its high intrinsic mobility, germanium (Ge) is a promising candidate as a channel material (offering a mobility gain of approximately × 2 for electrons and × 4 for holes when compared to conventional Si channels). Ho wever, man y issues still need to be addressed before Ge can be implemented in high-performance field-effect-transistor (FET) devices. One of the key issues is to provide a high-quality interfacial layer, which does not lead to substantial drive current degradation in both low equiv alent oxide thickness and short channel regime. In recent years, a wide range of materials and processes have been in vestigated to obtain proper interfacial properties, including different methods for Ge surface passiv ation, various high- k dielectrics and metal gate materials and deposition methods, and different post-deposition annealing treatments. It is observed that each process step can significantly affect the overall metal–oxide–semiconductor (MOS)-FET device performance. epi-Si passivation, surface oxidation and/or nitridation, and S-passi vation) with various high- k dielectrics. In particular, plasma-based processes for surface passiv ation in combination with plasma-enhanced atomic layer deposition for high- k depositions are shown to result in high-quality MOS structures. T o further improve properties, the gate stack can be annealed after deposition. The effects of annealing temperature and ambient on the electrical properties of the MOS structure are also discussed. (Some figures may appear in colour only in the online journal) 1. Introduction After continuously pursuing higher performance complementary metal–oxide–semiconductor field-effect- transistor (CMOSFET) devices for more than four decades, the conventional gate insulator SiO 2 is running out of atoms to retain the gate leakage current density ( J g) in an acceptable range [ 1]. Hafnium-based high-permittivity ( k) materials were introduced to replace SiO 2, since they can offer a larger physical thickness while maintaining a low equiv alent oxide thickness (EOT) due to their higher k value [ 2]. T h es w i t c ht o high- k dielectrics has reduced the significance of the SiO 2 / Si interface, and therefore of Si as the primary channel material. During the last decade, high-mobility channel materials 0268-1242/12/074012 + 14$33. 00 1 © 2012 IOP Publishing Ltd Printed in the UK & the USA Semicond. 27 (2012) 074012 QX i e et al including Ge and III–V compound semiconductors have been extensively in vestigated to achieve higher dri ve current ( I d) at lower V DD for future logic devices [ 3 – 5]. Germanium has been reconsidered as a very promising alternative channel material for high-performance MOSFETs due to its intrinsic high mobilities for both electrons (3900 cm 2 V − 1 s − 1) and holes (1900 cm 2 V − 1 s − 1)[ 4]. When compared to III–V materials, the integration of Ge on Si appears more easily feasible, since selective epitaxial growth of SiGe has already been implemented for several technology nodes. The SiGe strain technique is using selectively grown SiGe in source and drain to create a compressive stress in the Si channel and hence to enhance the mobility of holes in p-MOSFETs. The smaller band gap of Ge (0. 66 eV) potentially allows for lower contact resistances compared to Si due to a reduced barrier height, and is therefore more suitable for voltage scaling [ 3]. However, several major challenges need to be addressed before the implementation of Ge can be seriously considered at an industrial scale. The most critical issue is obtaining a high-quality interface between Ge and the high- k dielectric. T wo other major weaknesses of Ge technology are the difficulty of activating a high density of n-type doping and enhanced I off leakage current due to the small band gap [ 3]. The n-type doping issue may be overcome by using laser annealing for dopant activation [ 6, 7]. Adopting quantum well FET structures with an additional phosphorus isolation layer can significantly decrease I off and achieve a healthy subthreshold slope of 97 mV/DEC [ 8]. This review mainly focuses on the critical issue of improving the interface properties at the capacitor level. A detailed discussion on the effect of interface properties on MOSFETs is not included. During the past decade, many approaches have been investigated to passi vate the Ge surface. Surface nitridation of Ge was an early attempt, since GeO x was usually considered as a poor and unstable oxide. Epitaxial Si passivation of Ge surfaces has been well established and high performances were demonstrated for p-MOSFET devices. S passivation was effective for III–V compound semiconductors and w as also investigated for Ge. Recently, GeO 2 interfacial layer (IL) exhibit promising properties as well. W e will review those passivation methods and summarize the results from the existing literature in section 2. The deposition of a high- k dielectric can be achieved by various methods, including physical vapor deposition (PVD) [ 9], molecular beam deposition (MBD) [ 10, 11], chemical vapor deposition (CVD) [ 12, 13], and atomic layer deposition (ALD) (thermal [ 14] and plasma [ 15, 16]). Among these techniques, ALD received great interest due to its intrinsic self- terminated growth nature. ALD is a cyclic deposition process that consists of sequential self-limited surface adsorption and reaction. It provides precise thickness control at the atomic level and excellent step cov erage, which makes it the dominant deposition technique for high- k dielectrics in current state- of-the-art MOSFET devices. Many properties need to be considered for a potential high- k dielectric candidate. The most critical aspects are to achieve a high k value, lar ge band gap and dielectric breakdown electrical field ( E BD), as well as sufficient conduction band offset (CBO) and valence band offset (VBO) with respect to the channel material. Al 2 O 3, H f O 2, Z r O 2 and TiO 2 are the most investigated materials for gate dielectrics. Al 2 O 3 possesses a very wide band gap (approaching SiO 2) but a low dielectric constant ( ∼ 9). The k value of T iO 2 is rather high ( ∼ 80), while unfortunately it shows almost a zero CBO with respect to Si or Ge. The small band gap and low E BD of TiO 2 are not promising and therefore, a single layer of TiO 2 is not considered suitable as a gate dielectric in MOS devices. HfO 2 and ZrO 2 are usually considered as the most promising gate dielectrics, since they offer the combined benefits of a high thermal stability, relati vely high k valu e ( ∼ 25) and E BD, proper wide band gap and large CBO and VBO. T o achieve high performance, thermal treatments, e. g., post-dielectric annealing (PDA) or post-metallization annealing (PMA) are necessary for MOS devices. Choosing proper annealing temperature and annealing ambient is very important to improve the interface quality without causing substantial degradation to other device properties (i. e. EO T increase). Correlated with the Ge surface passivation, v arious dielectric materials and annealing treatments will be reviewed and discussed in sections 2 and 3. 2. Ge surface passivation T o achieve ultimate scaling, one solution is to deposit dielectrics directly on Ge without incorporation of an IL, which typically has a much lower k value than regular high- k dielectrics and therefore degrades the overall EO T. A clean Ge (1 0 0) surface can be obtained by in situ heating the substrate to 360 ◦ C for 15 min to desorb the native oxide. A minimum EOT of 0. 75 ( ± 0. 1) nm was achiev ed with a 3. 1 nm HfO 2 dielectric and the capacitor exhibited a low J g of 4. 5 × 10 − 4 Ac m − 2 (at 1 V in accumulation) [ 17]. An HF vapor prior to zirconia deposition was employed and an extremely low EO T of 0. 5 nm MOS capacitor (MOSCAP) was demonstrated in Pt / ZrO 2 / Ge MOS devices [ 18, 19]. A ZrO 2 / La 2 O 3 bi-layer structure was investigated and a 0. 5 nm EOT was also reported in Pt/ZrO 2 (1 nm) / La 2 O 3 (6 nm) / Ge structure with J g in the range of 0. 01–1 A cm − 2 and D it in the range of ∼ 3 × 10 12 eV − 1 cm − 2, respectively [ 20]. Oh et al reported a low capacitance equivalent thickness (CET) of 1. 3 nm with little interfacial oxide and they obtained a low J g of ∼ 1 × 10 − 6 Ac m − 2 [ 21]. TiO 2 / HfO 2 [ 22, 23] and TiO 2 / Al 2 O 3 [ 24, 25] bi-layers were implemented for EOT scaling by utilizing a ultrathin layer (HfO 2 or Al 2 O 3) to provide sufficient CBO, while maintaining the benefit of high k value of TiO 2. However, generally, an IL either intentionally or unintentionally formed during the high- k dielectrics deposition process is necessary for achieving high electrical performance of Ge-based MOS devices [ 26 – 28]. In the following, we will discuss the four most commonly used approaches for creating thin ILs for passivation of Ge, i. nitridation, Si- based schemes, S-based passivation and GeO x gro wn through thermal, ozone- or plasma-assisted oxidation. 2 Semicond. 27 (2012) 074012 QX i e et al 2. 1. Nitride passivation layer Many approaches were investigated to form a stable and desirable IL with Ge surface nitridation. One of the most frequently used methods was thermal NH 3 treatment at various temperatures [ 12, 29 – 36]. Single GeO x N y [ 29, 32]o r Ge 3 N 4 [ 37] layers were attempted as gate dielectrics. However, since they possess a rather low k value, more reports were using GeO x N y [ 30, 31, 33 – 35]o rG e N x [ 38, 39] as a passivation layer, with another higher k dielectric on top. Otani et al reported a low D it of 4 × 10 11 eV − 1 cm − 2 at midgap using a 2 nm thick GeN x passivation layer [ 38], w h i l eal o w e r D it of 1. 8 × 10 11 eV − 1 cm − 2 was demonstrated with a slightly thicker ( ∼ 2. 4 nm) GeN x IL [ 39]. Since thermal NH 3 treatment usually requires rather high temperatures (i. > 500 ◦ C), plasma was often used to reduce the nitridation temperature and to limit the thermal budget. V arious plasma sources including electron cyclotron resonance [ 38], radio-frequency inductively coupled plasma [ 40, 41] and microwave plasma [ 42]w e r e employed to create reactive radicals, and hence reduce the substrate temperature required for formation of the passivation layer. Many nitrogen sources were in vestigated. H 2 / N 2 / Ar and H 2 / N 2 / NH 3 / Ar gas mixtures were employed to form a GeO x N y IL. It allows tuning the atomic ration of nitrogen to the total GeO x N y component concentration (N/GeON) [ 43 – 45]. NH 3 plasma was used for Ge surface nitridation in both ex situ [ 46] and in situ [ 40] modes. Kutsuki et al proposed a plasma nitridation of a preformed ultrathin GeO 2 layer and obtained an EOT of 1. 7 nm with D it around 3 × 10 11 eV − 1 cm − 2 [ 47]. Improved interfacial/electrical properties were demonstrated using nitrogen engineering with NO and/or NH 3 plasma [ 48]. A 1. 1 nm thick GeO x N y I Lw a sp r o v e dt ob ee f f e c t i v e by exposing the Ge surface to a sequential NH 3, O 2 and NH 3 plasma at 350 ◦ C[ 49]. An atomic N beam was also found to be a very promising Ge surface nitridation source [ 50, 51]. Chen et al achieved a minimum EOT of 0. 53 nm with J g of 1 × 10 − 4 Ac m − 2 at V FB + 1V[ 50]. The electrical properties of GeO x N y formed by atomic beams of N and O at 250 ◦ C were investigated by Houssa’ s group and a minimum EOT of 0. 8 nm using HfO 2 gate dielectrics was achie ved [ 52]. In addition to the typically used GeO x N y IL, other nitrides like T aON [ 53], AlN [ 54 – 56], HfN [ 56] and SiN [ 57, 58] were tested to passivate the Ge surface and some promising properties were demonstrated. Compared to GeO 2 and GeON IL, the capacitor with T aON IL exhibited a superior EOT, less C–V stretch out and no apparent C–V hysteresis even under very high gate voltage sweep ( − 4t o + 4V)[ 53]. Using AlN as a passivation layer resulted in a relativ ely larger D it ( > 1 × 10 12 eV − 1 cm − 2)[ 55]. Kim et al demonstrated a minimum EOT of 0. 8 nm and a midgap D it of 2 × 10 12 eV − 1 cm − 2 when using a 1–2 nm Hf 3 N 4 or AlN IL [ 56]. Xie et al reported a SiH 4 –NH 3 treatment, which forms an ultrathin (0. 6 nm) SiN IL for effective Ge surface passi vation with a D it of 8. 73 × 10 11 eV − 1 cm − 2 [ 57]. T o give an overv iew of the effects of N-based surface passiv ation on J g, a graph of J g as a function of EOT is drawn in figure 1. Si passivation layer Among many possible candidates, a passivation scheme with an ultrathin epitaxial layer of Si is currently the most developed approach for Ge-based devices [ 3, 8]. An EOT of 1. 35 nm and J g of 1. 16 × 10 − 7 Ac m − 2 at 1 V bias were obtained for the T aN / HfO 2 / Ge MOSCAPs with SiH 4 surface treatment [ 58]. A 140% enhanced hole mobility was reported when using a very thin Si layer ( ∼ a few monolayers) incorporation into the high- k / Ge interface by SiH 4 surface annealing at 400 ◦ C[ 59]. Bai et al demonstrated high-performance devices with a Si interlayer ( ∼ 1 nm) deposited at 580 ◦ Cu s i n gt h e SiH 4 gas diluted with Ar [ 60]. A stable IL was obtained through performing a rapid thermal annealing (RT A) in NH 3 ambient at 550 ◦ C for 2 min prior to HfO 2 dielectric deposition. Excellent midgap D it (7 × 10 10 eV − 1 cm − 2)a se s t i m a t e d by the Terman method w as achieved with a low EO T of 1. 24 nm. J g was also very promising and was of 5 × 10 − 7 Ac m − 2 at 1 V bias. A better control of Ge in-diffusion using a low-temperature (350 ◦ C versus 500 ◦ C) epitaxial silicon passivation process was observed in Mitard’ s group [ 61]. It shows that lowering the Si passiv ation layer deposition temperature is the key development to ward further gate stack scalability, and a 1. 05 nm EO T with a five-monolayer Si IL deposited at 350 ◦ C was demonstrated. Howev er, Ge surface segregation through the Si cap remained a major effect limiting the effectiveness of the thin epitaxial Si-capping layer scheme [ 62]. A better understanding has been developed about this segregation process and an alternativ e Si precursor Si 3 H 8 was chosen to further boost the device performance thanks to its higher reactivity and H coverage [ 62]. Intel reported a record high hole mobility of 770 cm 2 V − 1 s − 1 with scaled CET of 1. 45 nm for strained germanium QW-FET using a Si-cap layer [ 8]. An optimum Si-cap layer thickness of 0. 6 nm was discovered through the hole mobility ev aluation for the Ge p-FET devices [ 8]. Comparing Si cap layer thicknesses ranging from 0. 6 to 1. 4 nm, it was found that mobility improves with reducing thickness due to reduction in carrier spill-out although the D it is slightly higher (from 1. 8 × 10 11 eV − 1 cm − 2 to 9. 0 × 10 11 eV − 1 cm − 2). However, the mobility degrades severely without any Si cap layer due to the very high D it when the Ge surface is not properly passivated. Another Ge surface passivation approach with Si-based cap is the complete oxidation of the Si IL layer and converting it to SiO 2 [ 63 – 65]. Chen et al used PDA at 400 ◦ Ci nO 2 ambient to form a 0. 8 nm thick SiO 2 IL for gate first n-MOSFETs. An electron mobility of 201 cm 2 V − 1 s − 1 at 0. 5 MV cm − 1 after 550 ◦ C RT A process was obtained for the devices using Ti x La 1 − x O dielectrics, which exhibit a rather high k valu e of 45 at x ∼ 0. 67 [ 63]. An improved mobility of 304 cm 2 V − 1 s − 1 was demonstrated by switching to applying a scanned KrF laser annealing for implanted dopant activation instead of using RTA [ 64]. By applying laser annealing on both gate dielectrics and source/drain activation, the T aN / ZrO 2 / La 2 O 3 / SiO 2 on Ge n-MOSFETs shows a low EO T of 0. 95 nm and a promising electron mobility of 340 cm 2 V − 1 s − 1 at 1 MV cm − 1 [ 65]. 3 Semicond. 27 (2012) 074012 QX i e et al Figure 1. Comparison of J g at V FB ± 1 V with respect to the EOT using different surf ace passivation methods. 3. S passivation S passivation is interesting because it may provide a technique that is compatible for both Ge and III–V compound high mobility channels [ 66, 67]. A hetero-atom like sulfur can passivate the Ge(1 0 0) interface by restoring the Ge surface and creating a low defect band gap [ 68]. S passiv ation can be obtained by means of a wet treatment with (NH 4) 2 S solution [ 69, 70], or by reactions in the gas phase using H 2 S[ 68, 71, 72], or elemental S [ 73, 74]. Ge–S–Ge bridges are formed after exposing the Ge surface to elemental S and can result in a (1 × 1) Ge surface reconstruction for 1 monolayer sulfur coverage [ 73]. Howe ver, large surface states in the Ge ener gy band gap were reported by using this technique, which rendered the elemental S passivation less desirable for high performance MOSEFT devices [ 74]. Frank et al demonstrated a well-passivated Ge surface using aqueous (NH 4) 2 S. A less than 3 monolayer thick, air- stable GeS x layer was formed with (1–2) × 10 15 cm − 2 Sa t o m s incorporation [ 69]. The sulfur passivation can be preserved substantially after high- k dielectrics (HfO 2) growth. Howe ver, the D it extracted by conductance method was still in relatively large value of 2. 4 × 10 12 eV − 1 cm − 2 [ 69]. Xie et al immersed the Ge substrates into 20% aqueous (NH 4) 2 S solution for 30 min at room temperature after a cyclic rinsing between de-ionized (DI) water and diluted HF [ 70]. The samples were subjected to a PMA at 450 ◦ C and a final FGA at 420 ◦ C for 2 h, and exhibited a D it of 4. 8 × 10 11 eV − 1 cm − 2 and a high stability up to 550 ◦ CP M A[ 70]. Sioncke et al obtained a S-terminated Ge(1 0 0) surface by dipping the wafers in a( N H 4) 2 S solution (25 wt%) for several minutes at room temperature followed by a water rinse [ 71]. The resulting D it near the midgap was around 10 12 eV − 1 cm − 2 when using Al 2 O 3 dielectrics. The D it increased to 10 13 eV − 1 cm − 2 when using HfO 2 or ZrO 2 dielectrics [ 71]. Houssa et al reported a study of the bonding geometry of a Ge(1 0 0) surface after exposure to H 2 Si nt h eg a s phase at 330 ◦ C, which showed evidence for 1 monolayer S coverage with (2 × 1) surface reconstruction [ 68]. The authors also conducted first-principle molecular dynamics simulations to confirm the preserved (2 × 1) reconstruction after dissociative adsorption of H 2 S molecules on a Ge(1 0 0) (2 × 1) surface and showed that this atomic configuration prevents surface states based on the computed energy band gap [ 68]. However, although the Ge–S interface is rather stable, it is still sensitive to oxygen compounds. H 2 O needed to be avoided for the high- k dielectric deposition [ 68, 72]. Merckling et al investigated the molecular beam passi vation of Ge(1 0 0) by molecular H 2 S and studied the adsorption of sulfur and the reorganization of the surface with reflection high-energy electron diffraction (RHEED) and x-ray photo- electron spectroscopy (XPS) [ 72]. The RHEED analysis can be used to monitor the atomic surface reconstruction in real time. The authors revealed that the RHEED pattern progressiv ely showed a streak (2 × 1) surface reconstruction by increasing the Ge substrate temperature up to 750 ◦ C in an ultra-high vacuum (UHV) MBE system, which indicated the complete de-oxidation of Ge(1 0 0). The RHEED diagrams after H 2 S exposure confirmed a good morphology of the H 2 S/Ge surface. However, a rather high D it of 5 × 10 12 eV − 1 cm − 2 near the midgap was still observed after the deposition of a 2 nm thick Al 2 O 3 dielectrics [ 72]. 4. GeO 2 passivation layer Native oxide of Ge was generally considered to be undesirable because it is hygroscopic and water soluble. GeO 2 is thermally unstable and converts to volatile GeO a t approximately 430 ◦ C. However, high-quality GeO 2 has recently been reconsidered as a promising passivation layer due to its extremely low D it ( ∼ 6 × 10 10 eV − 1 cm − 2)[ 75] and its potential to enable high performance Ge n-MOSFETs [ 76]. As Lee et al reported recently, peak electron mobility about 1100 cm 2 V − 1 s − 1 can be achieved on Ge n-MOSFETs using 4 Semicond. 27 (2012) 074012 QX i e et al rather thick GeO 2 dielectrics ( ∼ 20 nm), which was formed by high pressure (70 atm) oxidation at 550 ◦ C/10 min followed by a low-temperature oxygen annealing at 400 ◦ C[ 77, 78]. Kuzum et al demonstrated a ∼ 1. 5 times higher mobility than the universal Si mobility with a GeO 2 passiv ation layer formed by ozone oxidation, followed by ALD of an Al 2 O 3 dielectric [ 79]. Morii et al used a thermal oxidation process at 550 ◦ C for 20 min to form a GeO 2 passivation layer prior to the deposition of 20 nm of Al 2 O 3, and they achieved a high electron mobility of 804 cm 2 V − 1 s − 1 for n-MOSFET [ 80]. Although very promising electron mobility (higher than universal Si mobility) can be experimentally demonstrated for GeO 2 - based n-MOSFET, the thickness of GeO 2 w as rather large and resulted in a relatively large EO T and, correspondingly, less promising drive current ( I d). Apparent degradation was usually observed when the GeO 2 thickness was reduced [ 3], i. an electron mobility of 265 cm 2 V − 1 s − 1 was reported by Bellenger’s group when reducing the GeO 2 IL to 1. 2 nm [ 81]. Different approaches have been employed to form a high- quality GeO 2 IL and to provide proper Ge surface passivation. Thermally grown GeO 2 was extensi vely investigated considering different growth temperature and time [ 82 – 92]. Delabie et al reported a low D it of 3 × 10 11 eV − 1 cm − 2 with a thin thermally grown GeO 2 ( ∼ 1. 3 nm) IL (the total EOT of 1. 5 nm combined with a 4 nm HfO 2 dielectric or 2. 4 nm with a 4 nm Al 2 O 3 dielectric) [ 82]. Matsubara et al conducted Ge thermal oxidation at 450, 500, 550, 575 and 600 ◦ C and found that minimum D it (lower than 10 11 eV − 1 cm − 2) can be obtained for an oxidation temperature around 575 ◦ C with a rather thick GeO 2 of 30. 9 nm [ 89]. Xie et al performed a Ge thermal oxidation at 400 ◦ C and formed a 2 nm GeO 2. With a combination of a subsequent CF 4 plasma treatment after the HfO 2 gate dielectrics deposition, the structure exhibited a low D it of 2. 02 × 10 11 eV − 1 cm − 2 [ 90]. An effective hole mobility of 260 cm 2 V − 1 s − 1 was obtained for p-MOSFETs using a 1. 5 nm of GeO 2 passivation layer, which was thermally grown at 450 ◦ C in dry oxygen ambient [ 91]. A peak hole mobility of 396 cm 2 V − 1 s − 1 has been demonstrated when using this thermal O 2 passivation technique [ 92]. Ozone oxidation provides an alternative method to form a high quality GeO 2 IL [ 93, 94]. The minimum D it of 3 × 10 11 eV − 1 cm − 2 was demonstrated using ozone oxidation at 400 ◦ C[ 94]. Oxidation of the Ge surface with atomic oxygen has also been reported [ 95, 96]. Molle et al found that 300 ◦ C is the optimum temperature in terms of maximum GeO 2 oxide component. It was revealed that although the oxidation of the Ge substrate occurred already at room temperature, the formation of a GeO 2 layer was significantly enhanced at 300 ◦ C. Larger concentration of suboxide species formed at lower temperature, while the transformation of GeO 2 into suboxides sets in at temperatures higher than 300 ◦ C[ 96]. Baldovino et al systematically investigated the influence of the oxidizing species (ozone, molecular oxygen and atomic oxygen) on the Ge dangling bonds at the G e ( 100) / GeO 2 interface [ 97]. They revealed that the nature of the oxidizing species affects the interface microstructure, inducing wavefunction modifications and producing additional trapping centers. Figure 2. Comparison of D it at midgap with respect to the EOT according to different methods for the growth of germanium oxide. O 2 plasma treatment is a very promising approach to form low defect GeO 2 / Ge interfaces and GeO 2 IL at low substrate temperatures, due to the highly reactive O radicals [ 15, 98]. Fuduka et al demonstrated extremely low midgap D it of 4. 5 × 10 10 eV − 1 cm − 2 for Ge-based MOSCAPs with an electron-cyclotron-resonance plasma-formed GeO 2 (5 nm) IL [ 98]. The band gap of GeO 2 was determined by internal photoemission measurements to be 4. 7 eV with a CBO of 1. 8 eV and a VBO of 2. 2 eV at the GeO 2 / Ge interface [ 98]. Figure 2 summarizes some existing methods for germanium- oxide-based passivation by drawing D it as a function of EO T. Thermal, ozone- and plasma-based oxidation have been investigated in most detail. Alternati ve techniques have also been explored, e. g., deposition of a GeO 2 IL by RF sputtering [ 76, 99], or oxidation of the Ge surface using H 2 O prepulsing prior to dielectric deposition. The latter approach resulted in a surface layer with ∼ 70% hydroxyl termination, which appeared to produce a less-defective interfacial region [ 100]. It should be noted that besides these four most commonly used passivation methods, other approaches hav e also been explored, e. g., CeO 2 [ 101 – 103], La 2 O 3 [ 104], Y 2 O 3 [ 105], SnGeO x [ 106] as passivation layers, as well as a submonolayer coverage of barium [ 107]. Howe ver, it appears that the MOSFETs with CeO 2 / HfO 2 gate stacks exhibited reduced carrier mobility (electron ∼ 90 cm 2 V − 1 s − 1 and hole ∼ 3c m 2 V − 1 s − 1) compared to the devices with GeO 2 / HfO 2 gate stacks [ 102]. Considering the promising low thermal budget nature of plasma-based surface passivation, in the remainder of this review, we will discuss two specific cases of using in situ plasma surface treatments for Ge-based MOSCAPs. Cases For the following experiments, Ge(1 0 0) wafers with a resistivity of ∼ 0. 1 cm were used as substrates. Ge wafers were cleaned in a 0. 5% HF solution for 1 min followed by a 5 min rinse in DI H 2 O. The Ge surface passivation and subsequent high- k dielectrics deposition were conducted 5 Semicond. 27 (2012) 074012 QX i e et al Figure 3. C – V hysteresis characteristics for the Pt / HfO 2 / p-Ge MOSCAP without surface passivation. in a home-made ALD reactor with a base pressure less than 6 × 10 − 8 mbar [ 108, 109]. An inductively coupled plasma source (remote mode, downstream configuration) with the RF power up to 600 W was used for generating the plasma. Samples remain stationary in the ALD chamber during the surface treatment and ALD process, while the plasma source was separated from the ALD chamber through a computer-controlled valve during the precursor pulse to avoid contamination of the plasma source. The precursor was Tetrakis(eth ylmethylamido)hafnium (IV) (TEMAH) for the growth of HfO 2. For the fabrication of MOSCAPs, a shadow mask was used to pattern sputtered Pt gate electrodes. A Ti(2 0 nm) / Pt(40 nm) bi-layer structure was employed as a back electrode to reduce the series resistance. Case 1: comparison of GeO 2 and GeO x N y passivation layers Figure 3 shows the C – V hysteresis characteristics for the Pt/HfO 2 / p-Ge MOSCAP without surface passivation measured at 1 MHz. A very large hysteresis of ∼ 900 mV was observed at the flat-band voltage ( V FB), which indicates a very high density of slow traps and is consistent with previous reports [ 82, 84]. Because HfO 2 was grown by PE-ALD, the O 2 plasma during the initial ALD cycles may have induced an intermixing reaction with the uncovered Ge surface prior to the formation of a continuous HfO 2 film, resulting in bulk traps (slow traps). In situ synchrotron-based XRF and GIXAS results also show that there is no inhibition period of ALD high k on oxidized Ge surface, while H-terminated Ge has [ 110]. This inhibition probably indicates a poorly defined interface between Ge and high- k layers. It was also reported that slow traps can be attributed to Ge out-diffusion, resulting in intermixing of GeO x and HfO 2 [ 82, 84]. The poor hysteresis results support the necessity of a proper passivation layer for Ge-based MOSCAPs. Figure 4 demonstrates substantial C – V hysteresis reduction by using either a GeO 2 or a GeO x N y passivation ( a) ( b) ( c) Figure 4. C – V hysteresis characteristics for the Pt-gated MOSCAPs with HfO 2 high- k dielectrics and ( a)O 2 plasma passivation on p-Ge, ( b)N H 3 plasma passivation on p-Ge and ( c)O 2 passivation on n-Ge. 6 Semicond. 27 (2012) 074012 QX i e et al ( a) ( b) Figure 5. XPS Ge 3d spectra for the samples with ( a) GeO 2 and ( b) GeO x N y passivation layers. Both samples were capped by a 1 nm Al 2 O 3 cap to protect them during transport from the ALD chamber to the XPS system. layer. T o form a GeO 2 passivation layer, the Ge wafers were exposed to an O 2 plasma at 200 W with a partial pressure around 1 × 10 − 3 mbar prior to HfO 2 deposition. The GeO x N y passivation layer was formed by exposing to an NH 3 plasma with a pressure around 5 × 10 − 3 mbar at the same RF plasma power. There was no air exposure between the Ge surface passivation treatment and the high- k dielectrics ALD process. The passivation occurs ‘ in situ ’, which is expected to limit degradation due to air exposure, and hence enhance its performance. The sample temperature remained at 250 ◦ C, both for the plasma passivation and during the subsequent plasma-enhanced ALD growth of the high- k layer. By using either O 2 or NH 3 plasma treatment, much lo wer hysteresis (from 900 to 50 mV) was obtained although the HfO 2 deposition was similar when compared to the MOSCAP without passivation (figure 3), illustrating the effecti veness of the GeO 2 or GeO x N y passivation layers. Further characterizations were employed to analyze the nature of the passivation layer. Figure 5 shows XPS Ge 3d spectra for the two different passiv ation layers. An ultrathin Al 2 O 3 layer ( < 1n m)w a s in situ g r o w nb yP E - A L Do nt h e passivation layers prior to the XPS measurement to protect the IL from exposing to air directly. The XPS data shown in figure 5 ( a) indicate a binding energy (BE) shift of 3. 4 eV with ( a) ( b) Figure 6. XPS Ge 3p spectra for the samples with GeO 2 passivation layer ( a) with a 1 nm Al 2 O 3 capping layer, and ( b) with ∼ 5n mo f PE-ALD HfO 2 dielectrics. respect to Ge bulk. No apparent Ge suboxides were detected, indicating that the major component of the IL was Ge 4 +. I t is believed that the quality of the GeO x -based passiv ation layer is strongly affected by the oxidation states of the IL, and GeO 2 provides the most promising passivation properties [ 3, 82 – 84]. The high quality of GeO 2 formed by O 2 plasma is related to the high reactivity of O radicals created by the plasma. Different from the GeO 2 IL, the XPS data from the GeO x N y layer contained several subcomponents. In addition to a doublet attributed to bulk Ge 3d 3/2 and 3d 5/2, the spectra were deconvoluted into three components: GeO, GeO 2 and GeO x N y. Except for the GeO x N y, the chemical shifts of Ge 3d BE for each of these components were fixed according to the reported data [ 111]. The atomic concentration of N in the IL is around 8% according to the XPS measurement. It is difficult to tune the O/N ratio using our setup when performing NH 3 plasma treatment. Other authors reported a larger degree of tuning flexibility by using a H 2 / N 2 / Ar and H 2 / N 2 / NH 3 / Ar gas mixture plasma [ 43 – 45]. The influence of the high- k dielectric on the properties of the IL is important and affects the overall performance. Because Ge 3p has no overlap with Hf or O peaks, it was selected for the XPS analysis after the deposition of HfO 2 dielectrics. As shown in figure 6 ( a), in addition to a component of AlO x (Al 2s signal from the Al 2 O 3 cap layer), 7 Semicond. 27 (2012) 074012 QX i e et al two doublets related to bulk Ge and Ge oxides were fitted for the Ge 3p spectra. The chemical shift of the BE is ∼ 3 eV and is corresponding to the GeO 2 component. This result is consistent with the analysis from the Ge 3d spectra (figure 5 ( a)). However, a slight reduction of the GeO 2 IL was observed after HfO 2 deposition (without considering the reduction effect of sputtering HfO 2 for XPS sample preparation). W e fitted the Ge 3p spectra also with two doublets for the sample with HfO 2 dielectrics on the top. Although the IL retains its GeO 2 nature mostly and the atomic ration of Ge/O is close to 1:2, the BE shift is reduced to ∼ 2. 8 eV, indicating some degradation of the layer. The shift is smaller than that for Ge 4 + (3 eV) while larger than for Ge 3 + (2. 5 eV), indicating a certain amount of suboxides. It is believed that the degradation is partly due to the subsequent HfO 2 deposition process, which caused partial intermixing of the GeO 2 and HfO 2. Also, the sputtering during XPS measurement could partially contribute to the forming of this Ge suboxide. Similarly, for the GeO x N y passivation layer, the binding energy shift of Ge 3p core level was ∼ 2e Vp r i o rt oH f O 2 deposition and ∼ 1. 7 eV after HfO 2 deposition, also suggesting partial intermixing between the GeO x N y layer and the subsequent HfO 2 film. It appears that Al 2 O 3 is more compatible with the GeO 2 or GeO x N y IL because it induces no apparent IL degradation (figures 5 ( a) and 6 ( a)). Unfortunately, Al 2 O 3 has a relati vely low dielectric constant ( ∼ 9), limiting its usefulness as a high- k dielectric. The frequency dependent C – V characteristics of Pt / HfO 2 / GeO 2 / p-Ge and Pt / HfO 2 / GeO 2 / n-Ge capacitors after FGA at 350 ◦ C/30 min are shown in figures 7 ( a) and ( b), respectively. The thickness of HfO 2 and GeO 2 are around 3 and 1. 3 nm for both capacitors. W ell-behaved C – V curves were obtained on both types of Ge substrates without severe frequency dispersion. The C–V data indicate in version behavior with minority carrier response at low frequencies and a flat C min at 1 MHz. This indicates the efficient electrical passivation of the Ge interface by using a GeO 2 IL. D it was calculated based on the high-low frequency method [ 112] and the Berglund integral method was used to relate the gate voltage to the corresponding surface potential [ 113]. D it is around 3. 5 × 10 11 eV − 1 cm − 2 at V FB conditions for both capacitors. Similar C – V characteristics were observed for the MOSCAPs using GeO x N y IL, as reported in [ 40], although those samples exhibited slightly larger stretch out and dispersion of the C – V curves, indicating a higher D it. The estimated D it was around 6 × 10 11 eV − 1 cm − 2 under V FB conditions, which was roughly a factor of two times higher D it compared to the capacitors with GeO 2 IL. T o evaluate the contributions from the IL and high- k dielectric to the EOT, MOSCAPs with various thicknesses of HfO 2 were fabricated with a fixed GeO 2 IL thickness (fixed O 2 plasma pulse time at 30 s and power at 200 W). The EOT was estimated by the capacitance at strong accumulation, taking into account the quantum-mechanical effect. Based on the equation EOT = t IL + ( k SiO 2 / k ox) t ox, extrapolation suggests that the GeO 2 interlayer contributes t IL ∼ 0. 8 nm to the EOT, as shown in figure 8. The relative dielectric constant of HfO 2 ( k ox) was estimated based on the slope of the fitted line and a value of ∼ 24 was obtained. Apparently, ( a) ( b) Figure 7. C–V characteristics of HfO 2 on Ge(1 0 0) substrates with O 2 plasma passivation measured at various frequencies: ( a) Pt / HfO 2 / GeO 2 / p-Ge and ( b)P t / HfO 2 / GeO 2 / n-Ge. The thickness of HfO 2 and GeO 2 are ∼ 3 and 1. 3 nm, respectively. Figure 8. EOT versus HfO 2 thickness for the MOSCAP with a fix ed GeO 2 IL. the HfO 2 dielectric grown by PE-ALD approaches its bulk properties despite the thicknesses, which are in the nanometer range. It is found that when increasing the plasma pulse time from 30 to 60 s, a 0. 2 nm additional EOT contribution (1 nm instead of 0. 8 nm) from GeO 2 IL was observed. Unfortunately, the GeO 2 thickness does not scale with plasma exposure for pulse times smaller than 30 s, potentially limiting EOT scalability. A system with better control of the plasma 8 Semicond. 27 (2012) 074012 QX i e et al Figure 9. I – V characteristics of the MOSCAP with HfO 2 (3 nm) / GeO 2 (1. 3 nm) gate stacks on p-Ge. conditions may provide further GeO 2 thickness reduction without compromising the IL quality. F or the capacitors using GeO x N y IL, the EOT caused by the IL is ∼ 0. 6 nm and makes GeO x N y more desirable for scaling. However, introducing N into the IL also leads to larger D it, which is a significant drawback. V ery promising J g was obtained for the MOSCAPs with both GeO 2 and GeO x N y passivation layers. Figure 9 shows the I – V characteristics for the Pt / HfO 2 / GeO 2 / p-Ge capacitor with an EOT of 1. 3 nm. It exhibits a lo w J g ( ∼ 1 × 10 − 6 Ac m − 2) at V FB − 1 V, indicating high quality of the HfO 2 dielectrics (3 nm) grown by PE-ALD with low b ulk defects. Even lower J g (4 × 10 − 7 Ac m − 2)a t V FB − 1 V was demonstrated when using similar HfO 2 dielectrics on the GeO x N y IL [ 40]. An important property of dielectrics is their breakdown electric field ( E BD). W e stressed the MOSCAPs with high gate bias and evaluated E BD for the dielectrics. Figure 10 depicts the J g for the MOSCAPs with HfO 2 (3 nm) / GeO x N y (1 nm) gate stack, which had an EOT of 1. 1 nm. The drastic current increase for a bias below − 3 V is related to breakdown of the gate stack. For a bi-layer gate stack, with increasing V g, t h e GeO x N y IL was subject to a more rapidly increasing electric field due to its lower dielectric constant [ 40]. When V g was higher than 3. 1 V, E GeO x N y was greater than 15 MV cm − 1, causing breakdown of the GeO x N y IL. Then, the entire bias voltage was applied across the HfO 2 dielectric, and E HfO 2 was therefore larger than 8. 6 MV cm − 1 (which was substantially higher than its bulk E BD ∼ 6. 7 MV cm − 1 [ 114]), resulting in an immediate breakdown of the entire gate stack. For a GeO 2 IL, a lower E BD of ∼ 10 MV cm − 1 was observed. W e compared the MOSCAPs with both types of passivation and summarized the results in table 1. T h eG e O x N y IL shows Figure 10. I – V characteristics of the MOSCAP with HfO 2 (3 nm) / GeO x N y (1 nm) gate stacks on p-Ge. superior properties in terms of small EOT contribution, lo wer J g and larger E BD compared to GeO 2 IL. How ever, th e GeO 2 IL provides better D it. Case 2: effect of ALD process and PMA on MOSCAPs GeO 2 was reported to provide extremely low D it ( ∼ 6 × 10 10 eV − 1 cm − 2)[ 75] and therefore may enable high performance Ge n-MOSFETs [ 76]. However, GeO 2 is hygroscopic and sensitive to H 2 O. Therefore, the deposition process of high- k dielectrics may cause degradation on the GeO 2 IL if H 2 O was used as the oxygen reactant. In this section, we first investigated the properties of the MOSCAPs with thermally grown HfO 2 and compared them to PE-ALD-grown HfO 2. F o rG e O 2 -based capacitors, improved performances were reported recently by using annealing treatments in an oxidative ambient [ 115 – 117]. W e will present comparisons for the GeO 2 -based MOSCAPs after FGA and O 2 ambient annealing at various temperatures in the latter part of this section. Figure 11 depicts the C – V characteristics for the MOSCAPs with thermally grown HfO 2 dielectrics. The GeO 2 IL was formed by in situ O 2 plasma, as described in section 3. T h eG e O 2 / Ge interface properties remain promising ( D it ∼ 4 × 10 11 eV − 1 cm − 2 under the V FB condition) when compared to the capacitors with PE-ALD-grown HfO 2 and similar GeO 2 passivation layer. One apparent difference concerns the capacitance density, which is lower than that for a capacitor with the same HfO 2 thickness (8 nm) when it is grown by PE-ALD. The ev aluated k valu e of thermal ALD-grown HfO 2 is around 18, which is significantly lower than the value of HfO 2 grown by PE-ALD ( ∼ 24). This is probably related to the lower density of the thermally Ta b l e 1. Comparison of the MOSCAPs with different passivation treatment. Passivation Total EO T EOT D it C – VE BD J g (A cm − 2) treatment (with 3 nm HfO 2) contribution (10 11 eV − 1 cm − 2)h y s t e r e s i s @ V FB − 1V from IL O 2 plasma 1. 3 nm 0. 8 nm 3. 5 ∼ 50 mV 10 MV 1 × 10 − 6 NH 3 plasma 1. 1 nm 0. 6 nm 6 ∼ 50 mV 15 MV 4 × 10 − 7 9 Semicond. 27 (2012) 074012 QX i e et al Figure 11. C – V characteristics for the MOSCAPs with HfO 2 grown by thermal ALD using H 2 O. O 2 plasma was employed for Ge surface passivation. The structure of the sample is Pt/HfO 2 (8 nm) / GeO 2 (1. 5 nm) / p-Ge. Figure 12. C–V hysteresis characteristics for the Pt / HfO 2 / GeO 2 / p-Ge MOSCAP with HfO 2 grown by thermal ALD. grown HfO 2, as evidenced by x-ray reflectivity measurements. Although similar fast traps (interfacial traps, D it) densities were observed for the capacitors with HfO 2 dielectrics grown by either thermal or PE-ALD, the slow traps (bulk traps) densities were quite different. Slow traps (bulk traps) with time constant larger than 0. 01 s are too slow to respond to regular C – V measurement (typically form 100 Hz to 1 MHz). A C – V hysteresis measurement usually takes around 0. 1–1 s for each sweeping step and is therefore a useful technique to detect those slow traps. Figure 12 shows the C – V hysteresis characteristics for the Pt / HfO 2 / GeO 2 / p-Ge MOSCAP with HfO 2 grown by thermal ALD. A considerably larger hysteresis of ∼ 400 mV was observed (as compared to 50 mV shown in figure 4 ( a)), which may suggest more pronounced intermixing at the GeO 2 / HfO 2 interface for the H 2 O-based HfO 2 ALD process. The high C – V hysteresis is consistent with the report from [ 82, 84], which also used thermal ALD, and the capacitors exhibited low D it ( < 3 × 10 11 eV − 1 cm − 2) but lar ge hysteresis (200 ∼ 900 mV). In addition to the lower k value and higher bulk traps, the E BD of thermal ALD-grown HfO 2 was degraded. Figure 13 shows the comparison of the J g characteristics for the MOSCAPs with similar HfO 2 (8 nm) / GeO 2 (1. 5 nm) gate Figure 13. Comparison of I – V characteristics of the MOSCAP with HfO 2 (8 nm) / GeO 2 (1. 5 nm) gate stacks on p-Ge. GeO 2 was in situ formed by O 2 plasma, while HfO 2 was deposited by either thermal ALD or PE-ALD. Figure 14. C–V characteristics for the MOSCAPs with structure of Pt/HfO 2 (3 nm) / GeO 2 (1. 3 nm) / n-Ge. A 350 ◦ C/30 min PMA in O 2 ambient was employed. stacks but using different ALD processes for HfO 2 growth. A drastic J g increase was observed when the bias was ramped up to around − 4 V for the capacitor with thermally grown HfO 2. The capacitor with PE-ALD-grown HfO 2 exhibits a similar J g value at low electric field (from 0 to − 3V)b u t much lower J g at higher electric filed (from − 4t o − 3V). Furthermore, it demonstrates a higher dielectric break-down voltage ( < − 5. 1 V), which indicates a better quality of the HfO 2 dielectrics. Since the HfO 2 grown by PE-ALD possesses better properties, we will discuss further improvements with oxidative ambient annealing on PE-ALD HfO 2. The PMA was conducted in an O 2 / N 2 mixed ambient with 10% atomic concentration of oxygen [ 117]. The C – V characteristics for the Pt/HfO 2 (3 nm) / GeO 2 (1. 3 nm) / n-Ge sample annealed in O 2 ambient are shown in figure 14. The annealing temperature was 350 ◦ C and the total treatment time was 30 min. One distinction from the FGA sample (figure 7 ( a)) with identical structure and EOT is the considerable shift of the C – V curves, which indicates larger V FB after O 2 PMA. The evaluated V FB for the samples treated with FGA and O 2 PMA were 0. 5 and 0. 72 V, respectively. T o reveal the cause of the discrepancy of 10 Semicond. 27 (2012) 074012 QX i e et al Figure 15. Comparison of I – V characteristics of the MOSCAP with different annealing ambient. The samples structure is HfO 2 (5. 5 nm) / GeO 2 (1. 3 nm) / n-Ge with EOT of 1. 8 nm. V FB with different annealing treatment, we selected a series of samples with different HfO 2 thickness and treated them either with FGA or O 2 PMA. V FB and EOT were extracted based on C – V measurements for each sample. T wo V FB / EOT curves can be obtained for both annealing treatments because different HfO 2 thickness leads to different EOT [ 117]. The results suggest that the shift of V FB was due to a difference in fixed charges density for annealing in different ambient. The fixed charges density of the capacitor after FGA is 4. 5 × 10 12 cm –2, while the density is 8. 2 × 10 11 cm –2 after O 2 annealing, respectively. This indicates O 2 annealing is better suited to neutralize the fixed charges for the capacitors with GeO 2 -based IL. In addition to a lower density of fixed charges, O 2 PMA also provides better D it. Using the high-low frequency method, the evaluated D it after FGA and O 2 PMA were 4 × 10 11 and 2 × 10 11 eV − 1 cm − 2, respectively. Figure 15 compares J g for the capacitors after annealing in both ambients. Both capacitors exhibit excellent leakage current ( < 1 × 10 − 8 A cm − 2 at V FB + 1 V), while lower J g was achieved using O 2 PMA at large gate bias. Based on the aforementioned comparisons between FGA and O 2 ambient PMA, O 2 ambient PMA provides superior performance with better D it, smaller density of fixed charges and lower J g. One explanation is that O 2 annealing improves the GeO 2 IL by O diffusion through the HfO 2 dielectrics. It is noted that the effect of O 2 PMA is less pronounced for the MOSCAPs with GeO x N y IL. The properties of the GeO 2 -based MOSCAPs can be further improved by increasing the annealing temperature to 400 ◦ C. Figure 16 shows the C – V characteristics of the Pt- gated MOSCAPs with HfO 2 / GeO 2 gate stacks on n-type Ge substrates after PMA in O 2 ambient at 400 ◦ C / 30 min. It shows excellent behaved C – V curves (as-measured) with ne gligible stretch out and very limited dispersion in accumulation and depletion regions. The conductance method is a sensitive D it extraction technique developed for Si-based capacitors. It requires modifications to perform at increased temperatures for wide-band-gap semiconductors like GaAs [ 118] and decreased temperatures for small-band-gap semiconductors l i k eG eo rI n G a A s[ 119]. Low-temperature measurements were obtained through an HP4294 impedance analyzer with the samples placed in a cryostation [ 120]. Three Figure 16. C–V characteristics for the MOSCAPs with a PMA treatment in O 2 ambient for 400 ◦ C/30 min. Figure 17. Comparison of D it and EOT contribution of GeO 2 IL as a function of annealing temperatures. The annealing was conducted in O 2 ambient for 30 min. The thickness of HfO 2 and GeO 2 prior to annealing are 3 and 1. temperatures (77, 160 and 230 K) were selected for the D it extraction. Promising D it ( < 6 × 10 11 eV − 1 cm − 2)w a s obtained covering the entire measured energy lev els in the Ge band gap ( > 0. 51 eV) [ 117], and the D it remained low at both band edges (6 × 10 11 eV − 1 cm − 2 at E v side and 3 × 10 11 eV − 1 cm − 2 at E c side), which opens possibilities for GeO 2 -based CMOSFET devices. It should be mentioned that the relatively high annealing temperature is beneficial toward interfacial properties, but there is a penalty in the EO T. Figure 17 summarizes the D it and EOT contribution of the GeO 2 IL after different annealing temperatures in O 2 ambient. It reveals a decreasing trend in D it with increasing annealing temperatures. However, a concurrent increase was observed of the GeO 2 IL thickness. A ∼ 0. 2 nm higher EOT was found for the capacitor after 400 ◦ C annealing compared to the capacitors annealed at lower temperatures (i. < 360 ◦ C). A substantial EOT penalty was observed when the annealing temperature was increased to 450 ◦ C[ 116]. Even higher temperature (500 ◦ C) causes the formation of hafnium germanate and results in large density of interfacial traps [ 121]. Therefore, a temperature range from 350 to 400 ◦ C may be a proper temperature window for annealing GeO 2 -based MOS devices. 11 Semicond. 27 (2012) 074012 QX i e et al 4. Summary For high- k dielectrics on Ge, there is apparently no need for a dramatic change from conventional Si channel CMOSFET devices. ALD of Hf-based dielectrics is now well de veloped and most likely would work properly on a Ge channel as well. T o implement a Ge channel for MOSFET devices, one of the key issues is the Ge surface passiv ation. Many passivation methods have been extensi vely investigated and are sho wing promising progress. Generally, each approach has its o wn strengths and certain weaknesses. S-passivation is interesting because it is also a well-known passivation technique for III–V compound material channels (e. In 0. 53 Ga 0. 47 As). It can simplify process flow if hetero- structures are implemented, i. p-FET on the Ge channel and n-FET on an In 0. 47 As channel. One monolayer of S surface passivation is v ery promising for EOT scaling as well. However, further investigation is necessary to impro ve the interfacial properties by using S-passivation. Epi-Si is the most developed passiv ation technique and is compatible with the current CMOS process flow. An additional benefit of this method is that the band alignment of the Si / Ge(channel) / SiGe(buffer) structure intrinsically leads to a quantum well, which confines carriers in the Ge channel and is promising for QW-pFET de vices. However, it is still difficult to fabricate n-FET devices using epi-Si passiv ation due to the rather large D it at the E c side. A high-quality GeO 2 IL provides a possibility for both p and n-type Ge channel FETs. The main challenge is to maintain the high performance with reduced GeO 2 IL thickness, which is required to achieve sub-nanometer overall EO T. GeO x N y IL exhibits high E BD and is useful for some applications, which may require high voltages. The cases discussed in this paper illustrate that the use of plasma-based passivation, in combination with plasma-enhanced ALD may offer a promising route for achieving well-behaved MOS structures on Ge. After Ge surface passivation and high- k deposition, PDA/PMA is very useful to further improv e the performance with well-chosen annealing temperatures and ambient. Here, aside from the well-known forming gas anneal, annealing in oxygen ambient may be beneficial for reducing the fixed charge density in the gate stack. Acknowledgments The authors acknowledge the Bilateral Scientific and Technology Project Flanders, China, under Grant 01SB1809 and by the European Research Council under the European Union’s 7th frame work program (FP7/2007–2013) / ERC under grant agreement 239865. References [1] Wilk G D, W allace R M and Anthony J M 2001 J. Appl. Phys. 89 5243 [2] Choi J H, Mao Y and Chang J P 2011 Mater. Eng. R 72 97 [3] Caymax M et al 2009 IEEE T ech. Digest Int. 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The Ge 3p region is well deconvolved by two components [32] representing metallic Ge and a Ge oxide, with the 3/2 components at 122. 4 and 124. 7 eV, respectively (associated peaks at lower energies are the 1/2 components). The Sb 4p 3/2 peak presents a binding energy of 102. 6 eV, revealing an oxidized state of the adsorbed antimony, compatible with a +5 oxidation state [33, 34].... A new method for the creation of high-quality, fully electrically active junctions to be applied in nanostructured semiconductor materials is explored in this work. The method consists in a gas phase antimony deposition on Ge, which gives rise toan antimony self-limiting behavior to forma monolayer (ML) on the Ge (100) surface. The ML formation is characterized by a wide thermal process window in terms of time and temperature. Synchrotron radiation Angle Resolved X-Ray Photoelectron Spectroscopyshows that the ML structure consists in oxidized Sb grown over a very thin layer of Ge oxide, and a small amount of metallic Sb is embedded beneath the Ge surface during the deposition terestingly, during the ML formation process native Ge oxide is reduced without the need of strong acid pre-treatments. By performing further thermal annealing in equilibrium conditions, Sb diffusion can be faithfully described by a well assessed diffusion model. Finally, processing the Sb monolayer with Pulsed Laser Melting technique, which is a strongly out-equilibrium diffusion process, allows to exploit the entire Sb ML as a dopant source, thus achieving junctions with a very high dopant concentration (1. 2×10^(20) cm^(-3) Sb surface concentration) and a 100% Sb electrical activation. ****FREE DOWNLOAD USING THIS LINK (valid until 15 October 2019): ****... 38, 39 In contrast to ARTICLE the native oxide of Si which forms an excellent interface with Si and provides good passivation, GeO 2, the native oxide of Ge, is water soluble, i. e., offers poor protection, and forms a poor interface with Ge. [40][41][42] [43] Analogous to prior work on SiC based graphene growth, hydrogen intercalation at the graphene-Ge interface has been studied. 36, [44][45][46] The motivation being to preserve and tune the graphene-Ge interface for use in processes and devices where graphene directly supported on Ge is desired.... We explore a number of different electrochemical, wet chemical, and gas phase approaches to study intercalation and oxidation at the buried graphene-Ge interface. While the previous literature focused on the passivation of the Ge surface by chemical vapor deposited graphene, we show that particularly via electrochemical intercalation in a 0. 25 N solution of anhydrous sodium acetate in glacial acetic acid, this passivation can be overcome to grow GeO2 under graphene. Angle resolved photoemission spectroscopy, Raman spectroscopy, He ion microscopy, and time-of-flight secondary ion mass spectrometry show that the monolayer graphene remains undamaged and its intrinsic strain is released by the interface oxidation. Graphene acts as a protection layer for the as-grown Ge oxide, and we discuss how these insights can be utilized for new processing approaches.... Considering this, alternative technological progress to dimension scaling, such as changing channel material, is also necessary for achieving high performance devices [5]. Owing to its high intrinsic hole mobility, Ge has drawn remarkable attention for realizing high performance applications in the past decade [6, 7]. Ge-based metal-insulator-semiconductor (MIS) devices have shown great potential for integration into the Si CMOS technology, since promising electrical characteristics beyond those of Si devices could be realized by high-k/Ge structures [8].... In this paper, the impact of La2O3 passivation layers on the interfacial properties of Ge-based metal-insulator-semiconductor (MIS) structures was investigated. It was proven that the formation of a thermodynamically stable LaGeOx component by incorporating a La2O3 interlayer could effectively suppress desorption of the interfacial layer from GeO2 to volatile GeO. The suppression of GeO desorption contributed to the decrease in oxide trapped charges and interfacial traps in the bulk of the gate insulator, or the nearby interfacial regions in the Al2O3/La2O3/Ge structure. Consequently, the hysteretic behavior of the dual-swept capacitance-voltage (C-V) curves and the frequency dispersion of multi-frequency C-V curves were remarkably weakened. Besides, more than one order of magnitude decrease in the gate leakage current density, and higher insulator breakdown electric field were obtained after inserting a La2O3 passivation layer. In this work, the effects of different Dy-doping concentrations and annealing temperatures on the interfacial chemistry and electrical properties of TMA-passivated HfDyOx/Ge gate stacks have been investigated systematically. The microstructural, optical, interfacial chemistry, and electrical characteristics of sputtering-driven HfDyOx gate dielectrics have been characterized by means of X-ray diffraction (XRD), UV-Vis transmission spectroscopy, X-ray photoelectron spectroscopy (XPS), and electrical measurements. This work reveals that the interfacial chemistry evolution takes place via two competing processes, including oxide growth and oxide desorption. XPS analyses have confirmed that the 10 W-deposited targeted gate dielectrics display optimized interface characteristics, which can be attributed to the suppressed unstable Ge oxides and inhibition effects on inter-diffusion at the interface. Electrical observations show that the 10 W-driven HfDyOx/Ge MOS device without annealing treatment exhibits optimized electrical performance, including a larger permittivity of 22. 4, a smaller flat band voltage of 0. 07 V, vanishing hysteresis, a lowest oxide charge density of ∼10¹¹ cm⁻², and a lowest leakage current density of 2. 31 × 10⁻⁸ A cm⁻². Furthermore, the influences of doping and annealing conditions on the leakage current conduction mechanisms (CCMs) of HfDyOx/Ge MOS capacitors have also been investigated systematically. All of the experimental results indicate that TMA-passivated HfDyOx/Ge gate stacks with appropriate doping concentrations demonstrate potential application prospects for Ge-based MOSFET devices. Atomic layer deposition for nonconventional nanomaterials and their applications - Taewook Nam, Hyungjun Kim The growing of Internet has driven recent development of Silicon Photonics in the attempt of coping with the unceasing demand of bandwidth at cheap cost; datacentres with large footprint and enormous computational performances are deployed every year with a rate that, by 2021, will represent the 53% of the total count of installed servers. An ambitious yet necessary objective is envisioned by 2030, link speed above 1 Tb/s allowing sophisticated web-services to grow and reach users worldwide. Offering a fast, power efficient and easy to produce, integrated optic modulator working in the C and L band of the communication spectrum for datacentre applications, this thesis presents an innovative Franz-Keldysh based modulator, integrated in a rib waveguide on the 800 nm platform and fully CMOS compatible. The novelties of this design are found in the thick platform, which permits better optical confinement, and the wrap-around junction design that enables definition of wide rib while keeping strong electric field distribution in the active portion of the rib. Starting from a blank canvas, this project benefited from simulation study, process development and fabrication run. A simulation platform was, in fact, built to estimate electro-optic performances of design variations and define process recipes; the design reference was, then, translated in a set of masks used in the fabrication run. As a result, a device with cutting edge performances was realised, measuring dynamic extinction ratio of 5. 2 dB at 56 Gbps with 3dB bandwidth of 56 GHz. Scattering parameters measurements also permitted to evaluate a power consumption of 44 fJ/bit, confirming the exceptional electro-optical efficiency of the design. A side study investigating material engineering by means of rapid thermal annealing to tune the device absorption spectrum, that together with the possibility of customising the device design, permits to expand the operation bandwidth while supporting either the transverse electric or transverse magnetic polarisation, is also presented. In current manuscript, a Ge metal-oxide-semiconductor (MOS) capacitor based on HfGdON/Ge gate stacks with an ALD-driven passivation layer has been fabricated, and its interfacial and electrical properties are compared with those of its counterparts that have not undergone passivation treatment. Electrical analyses revealed that the HfGdON/Al2O3/Ge MOS device exhibits improved performance, including larger permittivity, negligible hysteresis, reduced flat band voltage, good capacitance–voltage behavior, and lower interface state and border trapped oxide charge density. All of these improvements can be ascribed to the suppressed growth of unstable Ge oxides, thus reducing the defective states at or near the HfGdON/Ge interface and improving the interface quality. In addition, detailed analyses of the current conduction mechanisms (CCMs) for Ge MOS capacitors with different passivation treatment were investigated systematically. Since the first development of large‐area graphene synthesis by the chemical vapor deposition (CVD) method in 2009, CVD‐graphene has been considered to be a key material in the future electronics, energy, and display industries, which require transparent, flexible, and stretchable characteristics. Although many graphene‐based prototype applications have been demonstrated, several important issues must be addressed in order for them to be compatible with current complementary metal‐oxide‐semiconductor (CMOS)‐based manufacturing processes. In particular, metal contamination and mechanical damage, caused by the metal catalyst for graphene growth, are known to cause severe and irreversible deterioration in the performance of devices. The most effective way to solve the problems is to grow the graphene directly on the semiconductor substrate. Herein, recent advances in the direct growth of graphene on group‐IV semiconductors are reviewed, focusing mainly on the growth mechanism and initial growth behavior when graphene is synthesized on Si and Ge. Furthermore, recent progress in the device applications of graphene with Si and Ge are presented. Finally, perspectives for future research in graphene with a semiconductor are discussed. For high-performance nanoscale Ge-based transistors, one important point of focus is interfacial germanium oxide (GeOx), which is thermodynamically unstable and easily desorbed. In this study, an atomic-layer-deposited AlN buffer layer was introduced between the crystalline ZrO2 high-K gate dielectrics and epitaxial Ge, in order to reduce the formation of interfacial GeOx. The results of X-ray photoelectron spectroscopy and high-resolution transmission electron microscopy demonstrate that the AlN buffer layer suppressed the formation of interfacial GeOx. Hence, significant enhancement of the electrical characteristics of Ge metal-oxide-semiconductor (MOS) capacitors was achieved with a two-orders-of-magnitude reduction in the gate leakage current, a 34% enhancement of the MOS capacitance, and a lower interfacial state density. The results indicate that the AlN buffer layer is effective in providing a high-quality interface to improve the electrical performance of advanced Ge MOS devices. The electrical and interfacial properties of atomic layer deposited AlN on p-Ge were investigated. A very large capacitance–voltage (C–V) hysteresis at 1 MHz was observed, resulted from the presence of high density of slow traps that is associated with the GeO volatilization. Nonetheless, well-behaved C–V characteristics with minimal frequency dispersion and the absence of bumps near the flat-band voltage were obtained except 1 MHz, implying that the AlN passivation occurred near the AlN/Ge interface. Parallel conductance values showed that both slow and fast states were located within a narrow energy range. X-ray photoelectron spectroscopy (XPS) spectra revealed that large amount of oxygen atoms are present near the AlN/Ge interface. Above the AlN critical thickness, the strong Al–Al bond in the Al 2p spectra was observed, which could be explained by the strain relaxation due to the lattice mismatch between AlN and Ge. The O-2 plasma pretreatment was investigated for passivation for HfO2 high-k Ge metal-oxide-semiconductor devices. With proper in situ O-2 plasma passivation, the capacitance-voltage hysteresis was substantially reduced from similar to 900 to similar to 50 mV for the HfO2/Ge gate stacks. Capacitors show well-behaved capacitance-voltage characteristics on both p-and n-type Ge substrates, indicating an efficient electrical passivation of the Ge interface. The interface trap density for both types of Ge substrates after passivation is below 4 x 10(11) eV(-1) cm(-2). A leakage current density of 1. 5 x 10(-7) and 2. 1 x 10(-8) A/cm(2) was obtained for the HfO2/p-Ge and HfO2/n-Ge capacitor with equivalent oxide thickness of 1. 8 nm at V-FB +/- 1 V, respectively. Material and electrical properties of TiO2/HfO2 bi-layer gate stacks were investigated for germanium (Ge) based metal-oxide-semiconductor devices. In situ NH3 plasma treatment was employed to passivate the Ge surface and promising performance including low capacitance-voltage hysteresis and interface trap density was achieved. It shows a superior dielectric breakdown voltage (4. 2-3. 4 V) for the TiO2/HfO2 bi-layer stacks than HfO2 single layer stack at a similar capacitance equivalent thickness (CET) of 1. 6 nm. A minimum CET of 1. 4 nm was obtained for capacitors on both p and n-type Ge (100) with a gate leakage current density < 4 x 10(-7) A/cm(2) at V-FB +/- 1 V. Chemical bonding states and electrical characteristics of a nitrided high-k/Ge gate stack formed as a compositional transition layer at TiO(2)/Ge interface has been examined. Thin TiO(2) have been deposited on p-type Ge (100) substrates by plasma enhanced CVD. The stoichiometry and chemical states are investigated by x-ray photoelectron spectroscopy. Depth profile XPS analyses revealed the formation of TiO(x)N(y) and GeO(x)N(y) after plasma nitridation. Peak decomposition technique was employed to identify the composition and the chemical states of the film. Stoichiometric TiO(2) observed at the surface layer is found to reduce to Ti-suboxides after Ar(+) ion sputtering. Plasma-assisted atomic layer deposition (ALD) is an energy-enhanced method for the synthesis of ultra-thin films with Å-level resolution in which a plasma is employed during one step of the cyclic deposition process. The use of plasma species as reactants allows for more freedom in processing conditions and for a wider range of material properties compared with the conventional thermally-driven ALD method. Due to the continuous miniaturization in the microelectronics industry and the increasing relevance of ultra-thin films in many other applications, the deposition method has rapidly gained popularity in recent years, as is apparent from the increased number of articles published on the topic and plasma-assisted ALD reactors installed. To address the main differences between plasma-assisted ALD and thermal ALD, some basic aspects related to processing plasmas are presented in this review article. The plasma species and their role in the surface chemistry are addressed and different equipment configurations, including radical-enhanced ALD, direct plasma ALD, and remote plasma ALD, are described. The benefits and challenges provided by the use of a plasma step are presented and it is shown that the use of a plasma leads to a wider choice in material properties, substrate temperature, choice of precursors, and processing conditions, but that the processing can also be compromised by reduced film conformality and plasma damage. Finally, several reported emerging applications of plasma-assisted ALD are reviewed. It is expected that the merits offered by plasma-assisted ALD will further increase the interest of equipment manufacturers for developing industrial-scale deposition configurations such that the method will find its use in several manufacturing applications. Metal-oxide-semiconductor capacitor was fabricated using in situ O2 plasma passivation and subsequent deposition of a HfO2 high-k gate stack on Ge. By extracting flat band voltages from capacitors with different equivalent oxide thicknesses (EOT), the effect of forming gas annealing (FGA) and O2 ambient annealing on the fixed charge was systematically investigated. The O2 ambient annealing is more effective than FGA as it reduced fixed charge density to 8. 3 × 1011 cm−2 compared to 4. 5 × 1012 cm−2 for at the same thermal budget and showed no degradation of EOT. Further, the distribution of fixed charges in gate stack was discussed in detail. Atomic layer deposited (ALD) HfO2/GeOxNy/Ge(1 0 0) and Al2O3/In0. 53Ga0. 47As(1 0 0) − 4 × 2 gate stacks were analyzed both by MOS capacitor electrical characterization and by advanced physical characterization to correlate the presence of electrically-active defects with chemical bonding across the insulator/channel interface. By controlled in situ plasma nitridation of Ge and post-ALD annealing, the capacitance-derived equivalent oxide thickness was reduced to 1. 3 nm for 5 nm HfO2 layers, and mid-gap density of interface states, Dit = 3 × 1011 cm−2 eV−1, was obtained. In contrast to the Ge case, where an engineered interface layer greatly improves electrical characteristics, we show that ALD-Al2O3 deposited on the In0. 47As (1 0 0) − 4 × 2 surface after in situ thermal desorption in the ALD chamber of a protective As cap results in an atomically-abrupt and unpinned interface. By avoiding subcutaneous oxidation of the InGaAs channel during Al2O3 deposition, a relatively passive gate oxide/III–V interface is formed. Atomic layer deposition (ALD) of TiO{sub 2} thin films using Ti isopropoxide and tetrakis-dimethyl-amido titanium (TDMAT) as two kinds of Ti precursors and water as another reactant was investigated. TiO{sub 2} films with high purity can be grown in a self-limited ALD growth mode by using either Ti isopropoxide or TDMAT as Ti precursors. Different growth behaviors as a function of deposition temperature were observed. A typical growth rate curve-increased growth rate per cycle (GPC) with increasing temperatures was observed for the TiO{sub 2} film deposited by Ti isopropoxide and H{sub 2}O, while surprisingly high GPC was observed at low temperatures for the TiO{sub 2} film deposited by TDMAT and H{sub 2}O. An energetic model was proposed to explain the different growth behaviors with different precursors. Density functional theory (DFT) calculation was made. The GPC in the low temperature region is determined by the reaction energy barrier. From the experimental results and DFT calculation, we found that the intermediate product stability after the ligand exchange is determined by the desorption behavior, which has a huge effect on the width of the ALD process window. The initial growth of HfO2 was studied by means of synchrotron based in situ x-ray fluorescence (XRF) and grazing incidence small angle x-ray scattering (GISAXS). HfO2 was deposited by atomic layer deposition (ALD) using tetrakis(ethylmethylamino)hafnium and H2O on both oxidized and H-terminated Si and Ge surfaces. XRF quantifies the amount of deposited material during each ALD cycle and shows an inhibition period on H-terminated substrates. No inhibition period is observed on oxidized substrates. The evolution of film roughness was monitored using GISAXS. A correlation is found between the inhibition period and the onset of surface roughness. Hafnium aluminate thin films were synthesized by atomic layer deposition (ALD) to assess the effect of aluminum oxide incorporation on the dielectric/Ge interfacial properties. In these HfAl{sub y}O{sub z} thin films, the Hf to Al cation ratio was effectively controlled by changing the ratio of hafnium oxide to aluminum oxide ALD cycles, while their short range order was changed upon increasing aluminum oxide incorporation, as observed by extended x-ray absorption fine structure analysis. The incorporation of aluminum oxide was shown to improve the electrical characteristics of hafnium oxide/Ge devices, including lower interface state densities and leakage current densities.
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Runtime - 1 h, 47 minutes Star - Ted Atherton.
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